Motorola MPC8260 PowerQUICC II User Manual page 427

Term
AAL ATM adaptation layer
ABR Availabe bit rate
ACR Allowed cell rate
ALU Arithmetic logic unit
APC ATM pace control
ATM Asynchronous transfer mode
BD Buffer descriptor
BIST Built-in self test
BT Burst tolerance
CBR Constant bit rate
CEPT Conference des administrations Europeanes des Postes et Telecommunications (European
Conference of Postal and Telecommunications Administrations).
C/I Condition/indication channel used in the GCI protocol
CLP Cell loss priority
CP Communications processor
CP-CS Common part convergence sublayer
CPM Communications processor module
CPS Cells per slot
CSMA Carrier sense multiple access
CSMA/CD Carrier sense multiple access with collision detection
DMA Direct memory access
DPLL Digital phase-locked loop
DPR Dual-port RAM
DRAM Dynamic random access memory
DSISR Register used for determining the source of a DSI exception
EA Effective address
EEST Enhanced Ethernet serial transceiver
EPROM Erasable programmable read-only memory
FBP Free buffer pool
FIFO First-in-Þrst-out (buffer)
GCI General circuit interface
GCRA Generic cell rate algorithm (leaky bucket)
GPCM General-purpose chip-select machine
MOTOROLA
Table vii. Acronyms and Abbreviated Terms
Part IV. Communications Processor Module
Part IV. Communications Processor Module
Meaning
Part IV-v