Siu Interrupt Priority Register (Siprr) - Motorola MPC8260 PowerQUICC II User Manual

Part II. ConÞguration and Reset
The SICR register bits are described in Table 4-4.
Bits Name
0Ð1 Ñ Reserved, should be cleared.
2Ð7 HP Highest priority. SpeciÞes the 6-bit interrupt number of the single interrupt controller interrupt source
that is advanced to the highest priority in the table. HP can be modiÞed dynamically. To retain the
original priority, program HP to the interrupt number assigned to XSIU1.
8Ð14 Ñ Reserved, should be cleared.
14 GSIU Group SIU. Selects the relative XSIU priority scheme. It cannot be changed dynamically.
0 Grouped. The XSIUs are grouped by priority at the top of the table.
1 Spread. The XSIUs are spread by priority in the table.
15 SPS Spread priority scheme. Selects the relative YCC priority scheme. It cannot be changed dynamically.
0 Grouped. The YCCs are grouped by priority at the top of the table.
1 Spread. The YCCs are spread by priority in the table.

4.3.1.2 SIU Interrupt Priority Register (SIPRR)

The SIU interrupt priority register (SIPRR), shown in Figure 4-11, deÞnes the priority
between IRQ1ÐIRQ6, PIT, and TMCNT.
Bits 0 1 2
Field XS1P
Reset 000
R/W
Addr
Bits 16 17 18
Field XS5P
Reset 100
R/W
Addr
Figure 4-11. SIU Interrupt Priority Register (SIPRR)
4-18
Table 4-4. SICR Field Descriptions
3 4 5 6
XS2P XS3P
001 010
19 20 21 22
XS6P XS7P
101 110
MPC8260 PowerQUICC II UserÕs Manual
Description
7 8 9 10
XS4P
011
R/W
0x10C10
23 24 25 26
XS8P
111
R/W
0x10C12
11 12 13 14
Ñ
0000
27 28 29 30
Ñ
0000
MOTOROLA
15
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