Motorola MPC8260 PowerQUICC II User Manual page 374

Part III. The Hardware Interface
CLKIN
A
RD/WR
D
PSDVAL
CS1
(RAS)
BS
(CAS)
GPL1
(OE)
cst1 1
cst2 1
cst3 0
cst4 0
bst1 0
bst2 0
bst3 0
bst4 0
g0l0
g0l1
g0h0
g0h1
g1t1 1
g1t3 1
g2t1
g2t3
g3t1
g3t3
g4t1
g4t3
g5t1
g5t3
redo[0]
redo[1]
loop 0
exen 0
amx0 0
amx1 0
na 0
uta 0
todt 0
last 0
PTS
Figure 10-82. Refresh Cycle (CBR) to EDO DRAM
10-98
0 0 0
0 0 0
0 0 0
0 0 0
0 1 1
1 1 1
1 1 1
1 1 1
1 1 1
1 1 1
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
PTS+1 PTS+2 PTS+3
MPC8260 PowerQUICC II UserÕs Manual
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
PTS+4
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9
Bit 10
Bit 11
Bit 12
Bit 13
Bit 14
Bit 15
Bit 16
Bit 17
Bit 18
Bit 19
Bit 20
Bit 21
Bit 22
Bit 23
Bit 24
Bit 25
Bit 26
Bit 27
Bit 28
Bit 29
Bit 30
Bit 31
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