Aal0 Protocol-Specific Rct - Motorola MPC8260 PowerQUICC II User Manual

Part IV. Communications Processor Module
Table 29-19. AAL1 Protocol-Specific RCT Field Descriptions (Continued)
Offset Bits Name
0x18 0Ð3 Ñ
4 SNEM
5Ð7 Ñ
8 RXBM
9Ð15 Ñ
29.10.2.2.4 AAL0 Protocol-SpeciÞc RCT
Figure 29-29 shows the layout for the AAL0 protocol-speciÞc RCT.
0 1
Offset + 0x0E
Offset + 0x10
Offset + 0x12
Offset + 0x14
Offset + 0x16
Offset + 0x18
Table 29-20 describes AAL0 protocol speciÞc RCT Þelds.
Table 29-20. AAL0-Specific RCT Field Descriptions
Offset Bits Name
0x0E 0-7 Ñ
8-9 0b01
10 INVE
11-15 Ñ
0x10 Ñ Ñ
29-50
Reserved, should be cleared.
Sequence number error ßag interrupt mask
0 This mode is disabled.
1 When an out-of-sequence error occurs, an RXB interrupt is sent to the interrupt
queue even if RCT[RXBM] is cleared. Note that this mode is the buffer error
reporting mechanism during automatic data forwarding (ATM-to-TDM bridging)
when no buffer processing is required (RCT[RXBM]=0).
Reserved, should be cleared.
Receive buffer interrupt mask
0 The receive buffer event of this channel is disabled. (The event is not sent to the
interrupt queue.)
1 The receive buffer event of this channel is enabled.
Reserved, should be cleared.
2 3 4 5 6
Ñ
Ñ
Figure 29-29. AAL0 Protocol-Specific RCT
Reserved, should be cleared.
Must be programmed to 0b01 for AAL0.
Inverted empty.
0 RxBD[E] is interpreted normally (1 = empty, 0 = not empty).
1 RxBD[E] is handled in negative logic (0 = empty, 1 = not empty).
Reserved, should be cleared.
Reserved, should be cleared.
MPC8260 PowerQUICC II UserÕs Manual
Description
7 8 9 10
0 1 INVE
Ñ
RXBM
Description
11 12 13 14 15
Ñ
Ñ
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