Siu Interrupt Pending Registers (Sipnr_H And Sipnr_L) - Motorola MPC8260 PowerQUICC II User Manual

Bits Name
3Ð11 YC2PÐYC8P Same as YC1P, but for YCC2ÐYCC8
12Ð15 Ñ

4.3.1.4 SIU Interrupt Pending Registers (SIPNR_H and SIPNR_L)

Each bit in the interrupt pending registers (SIPNR_H and SIPNR_L), shown in Figure 4-14
and Figure 4-15, corresponds to an interrupt source. When an interrupt is received, the
interrupt controller sets the corresponding SIPNR bit.
Bits 0 1
Field PC0 PC1
Reset
R/W
Addr
Bits 16 17
Field IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7
Reset UndeÞned (the user should write 1s to clear these bits before using)
R/W
Addr
1
These Þelds are zero after reset because their corresponding mask register bits are cleared (disabled).
Figure 4-15 shows SIPNR_L Þelds.
Bits 0 1 2
Field FCC1 FCC2 FCC3
Reset
R/W
Addr
Bits 16 17 18
Field I2C SPI RTT SMC1 SMC2 IDMA1 IDMA2 IDMA3 IDMA4 SDMA
Reset
R/W
Addr
1
These Þelds are zero after reset because their corresponding mask register bits are cleared (disabled).
MOTOROLA
Table 4-7. SCPRR_L Field Descriptions (Continued)
Reserved, should be cleared.
2 3 4 5
PC2 PC3 PC4 PC5
UndeÞned (the user should write 1s to clear these bits before using)
18 19 20 21
Figure 4-14. SIPNR_H Fields
3 4 5
Ñ MCC1 MCC2
19 20 21 22
Figure 4-15. SIPNR_L Fields
Chapter 4. System Interface Unit (SIU)
Description
6 7 8 9
PC6 PC7 PC8 PC9 PC10 PC11 PC12
R/W
0x10C08
22 23 24 25
R/W
0x10C10
6 7 8 9
Ñ SCC1 SCC2 SCC3 SCC4
1
0000_0000_0000_0000
R/W
0x10C0C
23 24 25
1
0000_0000_0000_000
R/W
0x10C0E
Part II. ConÞguration and Reset
10 11 12 13
PC13
26 27 28 29
Ñ TMCNT
1
0
10 11 12
26 27 28
Ñ TIMER1 TIMER2 TIMER3 TIMER4 Ñ
14 15
PC14 PC15
30 31
PIT Ñ
1 1
0 0
13 14 15
Ñ
29 30 31
1
0
4-21