Motorola MPC8260 PowerQUICC II User Manual page 294

Part III. The Hardware Interface
Table 10-4. ORx Field Descriptions (SDRAM Mode) (Continued)
Bits Name
27 IBID Internal bank interleaving within same device disable. Setting this bit disables bank interleaving
between internal banks of a SDRAM device connected to the chip-select line. IBID should be set
in 60x-compatible mode if the SDRAM device is not connected to the BANKSEL pins.
28Ð31 Ñ Reserved, should be cleared.
Figure 10-8 shows ORx as it is formatted for GPCM mode.
Bit 0 1 2
Field
Reset
R/W
Addr 0x10104 (OR0); 0x1010C (OR1); 0x10114 (OR2); 0x1011C (OR3); 0x10124 (OR4); 0x1012C (OR5);
0x10134 (OR6); 0x1013C (OR7); 0x10144 (OR8); 0x1014C (OR9); 0x10154 (OR10); 0x1015C (OR11)
Bit 16 17 18
Field ...AM Ñ
Reset 0 00
R/W
Addr 0x10106 (OR0); 0x1010E (OR1); 0x10116 (OR2); 0x1011E (OR3); 0x10126 (OR4); 0x1012E (OR5); 0x10136
(OR6); 0x1013E (OR7); 0x10146 (OR8); 0x1014E (OR9); 0x10156 (OR10); 0x1015E (OR11)
Table 10-5 describes ORx Þelds in GPCM mode.
Table 10-5. ORxÑGPCM Mode Field Descriptions
Bits Name
0Ð16 AM Address mask. Masks corresponding BRx bits. Masking address bits independently allows external
devices of different size address ranges to be used.
0 Corresponding address bits are masked.
1 The corresponding address bits are used in the comparison with address pins. Address mask bits
can be set or cleared in any order in the Þeld, allowing a resource to reside in more than one area
of the address map. AM can be read or written at any time.
Note: After system reset, OR0[AM] is 1111_1110_0000_0000_0.
17Ð18 Ñ Reserved, should be cleared.
19 BCTLD Data buffer control disable. Disables the assertion of BCTLx during access to the current memory
bank. See Section 10.2.7, ÒData Buffer Controls (BCTLx).Ó
0 BCTLx is asserted upon access to the current memory bank.
1 BCTLx is not asserted upon access to the current memory bank.
20 CSNT Chip-select negation time. Determines when CS/WE are negated during an external memory write
access handled by the GPCM. This helps meet address/data hold times for slow memories and
peripherals.
0 CS/WE are negated normally.
1 CS/WE are negated a quarter of a clock earlier.
Note: After system reset OR0[CSNT] is set.
10-18
3 4 5 6
1111_1110_0000_0000
19 20 21 22
BCTLD CSNT ACS
0 1 11
Figure 10-8. ORx ÑGPCM Mode
MPC8260 PowerQUICC II UserÕs Manual
Description
7 8 9 10 11
AM...
R/W
23 24 25 26 27
Ñ SCY
0 1111
R/W
Description
12 13 14 15
28 29 30 31
SETA TRLX EHTR Ñ
0 1 0 0
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