Motorola MPC8260 PowerQUICC II User Manual page 576

Part IV. Communications Processor Module
TCLK
TXD
(Output)
RTS
(Output)
CTS
(Input)
NOTE
:
1. GSMR_H[CTSS] = 0. CTSP=0 or no CTS lost can occur.
TCLK
TXD
(Output)
RTS
(Output)
CTS
(Input)
NOTE:
1. GSMR_H[CTSS] = 1. CTSP=0 or no CTS lost can occur.
Figure 19-11. CTS Lost in Synchronous Protocols
Note that if GSMR_H[CTSS] = 1, CTS transitions must occur while the Tx clock is low.
Reception delays are determined by CD as shown in Figure 19-12. If GSMR_H[CDS] is
zero, CD is sampled on the rising Rx clock edge before data is received. If GSMR_H[CDS]
is 1, CD transitions cause data to be immediately gated into the receiver.
19-20
First Bit of Frame Data
CTS Sampled Low Here
First Bit of Frame Data
MPC8260 PowerQUICC II UserÕs Manual
CTS Sampled High Here
CTS Lost Signaled in Frame BD
CTS Lost Signaled in Frame BD
Data Forced High
RTS Forced High
Data Forced High
RTS Forced High
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