Table of Contents
Advertisement
Rx
FCC1
Rx
FCC2
Rx
FCC3
Rx
SCC1
Rx
SCC2
Rx
SCC3
Rx
SCC4
SMC1
SMC2
The eight BRGs also make their clocks available to external logic, regardless of whether
the BRGs are being used by a serial device. Notice that the BRG outputs are multiplexed
with other functions; thus, all BRGOx pins may not always be available. Chapter 35,
ÒParallel I/O Ports,Ó shows the function multiplexing.
There are two restrictions in the bank-of-clocks mapping:
¥ Only four of the twenty sources can be connected to any given FCC or SCC receiver
or transmitter.
¥ The SMC transmitter and receiver share the same clock source when connected to
the NMSI.
Table 15-1 shows the clock source options for the serial controllers and TDM channels.
MOTOROLA
BRG5
BRG1
Tx
Tx
Tx
Tx
Tx
Tx
(Partially filled cross-switch logic
programmed in the CMX registers.)
Tx
Rx
Tx
Rx
Tx
Rx
TDMA1
TDMB1
TDMC1
Figure 15-3. Bank of Clocks
Chapter 15. CPM Multiplexing
Part IV. Communications Processor Module
BRG6
BRG7
BRG2
BRG3
BRG4
Bank of Clocks
Selection Logic
Tx
Rx
Tx
Rx
Tx
Rx
TDMD1
TDMA2
TDMB2
BRG8
BRGO5
BRGO6
BRGO7
BRGO8
BRGO1
BRGO2
BRGO3
BRGO4
CLK1
CLK2
CLK3
CLK4
CLK5
CLK6
CLK7
CLK8
CLK9
CLK10
CLK11
CLK12
CLK13
CLK14
CLK15
CLK16
CLK17
CLK18
CLK19
CLK20
Tx
Rx
Tx
Rx
Tx
TDMC2
TDMD2
15-5
Advertisement
Table of Contents
