Features; C Controller Clocking And Signal Functions - Motorola MPC8260 PowerQUICC II User Manual

Part IV. Communications Processor Module
2
The I C receiver and transmitter are double-buffered, which corresponds to an effective
two-character FIFO latency. In normal operation, the transmitter shifts the msb (bit 0) out
2
Þrst. When the I C is not enabled in the I
little power.

34.1 Features

The following is a list of the I
¥ Two-signal interface (SDA and SCL)
¥ Support for master and slave I
¥ Multiple-master environment support
¥ Continuous transfer mode for automatic scanning of a peripheral
¥ Supports a maximum clock rate of 2,080 KHz (with a CPM utilization of 25%),
assuming a 100-MHz system clock.
¥ Independent, programmable baud-rate generator
¥ Supports 7-bit I
¥ Open-drain output signals allow multiple master conÞguration
¥ Local loopback capability for testing
34.2 I

C Controller Clocking and Signal Functions

2
2
The I C controller can be conÞgured as a master or slave for the serial channel. As a master,
the controllerÕs BRG provides the transfer clock. The I
clock (BRGCLK), which is generated from the CPM clock; see Section 9.8, ÒSystem Clock
Control Register (SCCR).Ó
SDA and SCL are bidirectional signals connected to a positive supply voltage through an
external pull-up resistor. When the bus is free, both signals are pulled high. The general I
master/slave conÞguration is shown in Figure 34-2.
Figure 34-2. I
34-2
2
C mode register (I2MOD[EN] = 0), it consumes
2
C controllerÕs main features:
2
C operation
2
C addressing
Master
SCL
SDA
2
C Master/Slave General Configuration
MPC8260 PowerQUICC II UserÕs Manual
2 C BRG takes its input from the BRG
V DD
Slave
SCL
(EEPROM, for example)
SDA
V DD
2 C
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