Apc Data Structure - Motorola MPC8260 PowerQUICC II User Manual

Part IV. Communications Processor Module
Table 29-28. OAMÑPerformance Monitoring Table Field Descriptions
Offset Bits Name
0x00 0 FMCE
1 TSTE
2Ð4 Ñ
5Ð15 TCC
0x02 0Ð4 Ñ
5Ð15 BLCKSIZE
0x04 Ñ TUC1
0x06 Ñ TUC0
0x08 Ñ BEDC0+1-Tx Block error detection code 0+1Ðtransmitted cells. Even parity over the payload of the
0x0A Ñ BEDC0+1-RX Block error detection code 0+1Ðreceived cells. Even parity over the payload of the
0x0C Ñ TRCC1
0x0E Ñ TRCC0
0x10 0Ð7 Ñ
8Ð15 SN-FMC
0x12 Ñ Ñ
0x14 Ñ PMCH
0x18Ð Ñ Ñ
0x1E

29.10.4 APC Data Structure

The APC data structure consists of three elements: the APC parameter tables for the PHY
devices, the APC priority table, and the APC scheduling tables. See Figure 29-38.
29-61
Enables FMC transmission. Initialize to 1.
FMC time stamp enable
0 The time stamp Þeld of the FMC is coded with all 1Õs.
1 The value of the time stamp timer is inserted into the time stamp Þeld of the FMC.
Reserved, should be cleared.
TX cell count. Used by the CP to count data cells sent. Initialize to zero.
Reserved, should be cleared.
Performance monitoring block size ranging from 1 to 2,047 cells.
Total user cell 1. Count of CLP = 1 user cells (modulo 65,536) sent. Initialize to 0.
Total user cell 0. Count of CLP = 0 user cells (modulo 65,536) sent. Initialize to 0.
block of user cells sent since the last FMC. Initialize to 0.
block of user cells received since the last FMC. Initialize to 0.
Total received cell 1. Count of CLP = 1 user cells (modulo 65,536) received. Initialize
to 0.
Total received cell 0. Count of CLP = 0 user cells (modulo 65,536) received. Initialize
to 0.
Reserved, should be cleared.
Sequence number of the last FMC sent. Initialize to 0.
Reserved, should be cleared.
PM cell header. Holds the ATM cell header of the FMC, BRC to be inserted by the CP
into the Tx cell ßow.
Reserved, should be cleared.
MPC8260 PowerQUICC II UserÕs Manual
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