C Transmit Buffer Descriptor (Txbd) - Motorola MPC8260 PowerQUICC II User Manual

Part IV. Communications Processor Module
34.7.1.2 I 2

C Transmit Buffer Descriptor (TxBD)

Transmit data is arranged in buffers referenced by TxBDs in the TxBD table. The Þrst word
of the TxBD, shown in Figure 34-14, contains status and control bits.
0 1
Offset + 0 R Ñ
Offset + 2
Offset + 4
Offset + 6
Table 34-10 describes I
Table 34-10. I
Bits Name
0 R Ready.
0 The buffer is not ready to be sent. This BD or its buffer can be modiÞed. The CP clears R after the
buffer is sent or an error occurs.
1 The buffer is ready for transmission or is being sent. The BD cannot be modiÞed once R is set.
1 Ñ Reserved and should be cleared.
2 W Wrap (last BD in TxBD table).
0 Not the last BD in the table.
1 Last BD in the table. After this buffer is used, the CP transmits data using the BD pointed to by
TBASE (top of the table). The number of BDs in this table is determined only by the W bit and overall
space constraints of the dual-port RAM.
3 I Interrupt.
0 No interrupt is generated after this buffer is serviced.
1 I2CER[TXB] or I2CER[TXE] is set when the buffer is serviced. If enabled, an interrupt occurs.
4 L Last.
0 This buffer does not contain the last character of the message.
1 This buffer contains the last character of the message. The I
after sending this buffer.
5 S Generate start condition. Provides ability to send back-to-back frames with one I2COM[STR] trigger.
0 Do not send a start condition before the Þrst byte of the buffer.
1 Send a start condition before the Þrst byte of the buffer. (Used to separate frames.)
Note: If this BD is the Þrst one in the frame when I2COM[STR] is triggered, a start condition is sent
regardless of the value of TxBD[S].
6Ð12 Ñ Reserved and should be cleared.
13 NAK No acknowledge. Indicates that the transmission was aborted because the last byte sent was not
acknowledged. The I
14 UN Underrun. Indicates that the I
the associated buffer. The I
15 CL Collision. Indicates that transmission terminated because the transmitter was lost while arbitrating for
the bus. The I
34-14
2 3 4 5
W I L S
Figure 34-14. I
2
C TxBD status and control bits.
2
C TxBD Status and Control Bits
2
C controller updates NAK after the buffer is sent.
2
C controller encountered a transmitter underrun condition while sending
2
C controller updates UN after the buffer is sent.
2
C controller updates CL after the buffer is sent.
MPC8260 PowerQUICC II UserÕs Manual
6 7 8 9 10
Ñ
Data Length
Tx Buffer Pointer
2
C TxBD
Description
2
C controller generates a stop condition
11 12 13 14 15
NAK UN CL
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