Motorola MPC8260 PowerQUICC II User Manual page 549

Part IV. Communications Processor Module
Table 18-10. IDMA BD Field Descriptions (Continued)
Offset Bits Name
11 DGBL
12-13 DBO
14 Ñ
15 DDTB
0x02 0-1 Ñ
2 SGBL
3-4 SBO
5 Ñ
6 SDTB
7-15 Ñ
0x04 0Ð31 Data
Length
0x08 0Ð31 Source
Buffer
Pointer
0x0C 0Ð31 Destination
Buffer
Pointer
18-25
Destination global
0 Snooping is not activated.
1 Snooping is activated for write transactions to the destination.
In ßy-by mode, should be the same as SGBL.
Destination byte ordering:
01 PowerPC little Endian.
1x Big endian (Motorola).
00 Reserved
In ßy-by mode, should be the same as SBO.
Reserved, should be cleared.
Destination data bus.
0 The destination address lies within the 60x bus.
1 The destination address lies within the local bus.
In ßy-by mode, should be the same as SDTB.
Reserved, should be cleared.
Source global
0 Snooping is not activated.
1 Snooping is activated for read transactions from the source.
In ßy-by mode, should be the same as DGBL.
Source byte ordering:
01 PowerPC little endian
1x Big endian (Motorola)
00 Reserved
In ßy-by mode, should be the same as DBO.
Reserved, should be cleared.
Source data bus.
0 The source address lies within the 60x bus.
1 The source address lies within the local bus.
In ßy-by mode, should be the same as DDTB.
Reserved, should be cleared.
Number of bytes the IDMA transfers. Should be programmed to a value greater than
zero.
Notes: When operating with a peripheral that accepts only single bus transactions
(transfer size < 32), data length should be a multiple of the peripheral transfer size (STS
for S/D = 10, or DTS for S/D = 01). Also, there is no error notiÞcation if the data length
does not match the buffer sizes.
Holds the address of the associated buffer. Buffers may reside in internal or external
memory. Note that if the source/destination is a device, the pointer should contain the
device address.
In ßy-by mode, the pointers should contain the memory address.
MPC8260 PowerQUICC II UserÕs Manual
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