Motorola MPC8260 PowerQUICC II User Manual page 446

Part IV. Communications Processor Module
0x0000
Bank #1
BD/Data/µCode
2 KBytes
0x0800
Bank #2
BD/Data/µCode
2 KBytes
0x1000
Bank #3
BD/Data/µCode
2 KBytes
0x1800
Bank #4
BD/Data/µCode
2 KBytes
0x2000
Bank #5
BD/Data/µCode
2 KBytes
0x2800
Bank #6
BD/Data/µCode
2 KBytes
0x3000
Bank #7
BD/Data
2 KBytes
0x3800
Bank #8
BD/Data
2 KBytes
The dual-port RAM data bus is 64-bits wide. The RAM is used for six possible tasks:
¥ To store parameters associated with the FCCs, SCCs, MCCs, SMCs, SPI, I
IDMAs in the parameter RAM.
¥ To store buffer descriptors (BDs).
¥ To hold data buffers (optional because data can also be stored in external memory).
¥ For temporary storage of FCC data moving to/from an FCC FIFO (using the BTM)
from/to external memory (using SDMA).
¥ To store RAM microcode for the CP. This feature allows Motorola to add protocols
in the future.
¥ For additional scratch-pad RAM space for user software.
The RAM is designed to serve multiple requests at the same cycle, as long as they are not
in the same bank.
13-16
0x4000
Figure 13-8. Dual-Port RAM Memory Map
MPC8260 PowerQUICC II UserÕs Manual
Bank #1
BD/Data/µCode
2 KBytes
Bank #1
BD/Data/µCode
2 KBytes
Bank #1
BD/Data/µCode
2 KBytes
Bank #1
BD/Data/µCode
2 KBytes
Reserved
Bank #1
BD/Data/µCode
2 KBytes
Bank #1
BD/Data/µCode
2 KBytes
Bank #1
BD/Data/µCode
2 KBytes
Bank #1
BD/Data/µCode
2 KBytes
0x8000
Bank #9
Parameter RAM
2 KBytes
0x8800
Bank #10
Parameter RAM
2 KBytes
(Partially Reserved)
0x9000
Bank #11
BD/Data/µCode
2 KBytes
Bank #1
BD/Data/µCode
2 KBytes
Reserved
Bank #1
BD/Data/µCode
2 KBytes
Bank #1
BD/Data/µCode
2 KBytes
0xB000
Bank #11
FCC Data
2 KBytes
0xB800
Bank #12
FCC Data
2 KBytes
2
C, and
MOTOROLA