Features - Motorola MPC8260 PowerQUICC II User Manual

Part IV. Communications Processor Module
All standards provide handshaking signals, but some systems require only three physical
linesÑTx data, Rx data, and ground. Many proprietary standards have been built around
the UARTÕs asynchronous character frame, some of which implement a multidrop
conÞguration where multiple stations, each with a speciÞc address, can be present on a
network. In multidrop mode, frames of characters are broadcast with the Þrst character
acting as a destination address. To accommodate this, the UART frame is extended one bit
to distinguish address characters from normal data characters.
In synchronous UART (isochronous operation), a separate clock signal is explicitly
provided with the data. Start and stop bits are present in synchronous UART, but
oversampling is not required because the clock is provided with each bit.
The general SCC mode register (GSMR) is used to conÞgure an SCC channel to function
in UART mode, which provides standard serial I/O using asynchronous character-based
(start-stop) protocols with RS-232C-type lines. Using standard asynchronous bit rates and
protocols, an SCC UART controller can communicate with any existing RS-232-type
device and provides a serial communications port to other microprocessors and terminals
(either locally or via modems). The independent transmit and receive sections, whose
operations are asynchronous with the core, send data from memory (either internal or
external) to TXD and receive data from RXD. The UART controller supports a multidrop
mode for master/slave operations with wake-up capability on both the idle signal and
address bit. It also supports synchronous operation where a clock (internal or external) must
be provided with each bit received.

20.1 Features

The following list summarizes main features of an SCC UART controller:
¥ Flexible message-based data structure
¥ Implements synchronous and asynchronous UART
¥ Multidrop operation
¥ Receiver wake-up on idle line or address bit
¥ Receive entire messages into buffers as indicated by receiver idle timeout or by
control character reception
¥ Eight control character comparison
¥ Two address comparison in multidrop conÞgurations
¥ Maintenance of four 16-bit error counters
¥ Received break character length indication
¥ Programmable data length (5Ð8 bits)
¥ Programmable fractional stop bit lengths (from 9/16 to 2 bits) in transmission
¥ Capable of reception without a stop bit
¥ Even/odd/force/no parity generation and check
20-2 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA