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7.2.1.2.2 Bus Grant (BG)ÑOutput
Following are the state meaning and timing comments for the BG signal output in external
master mode.
State Meaning
Timing Comments AssertionÑMay occur on any cycle. Once the external device has
7.2.1.3 Address Bus Busy (ABB)
The address bus busy (ABB) signal is both an input and an output signal.
7.2.1.3.1 Address Bus Busy (ABB)ÑOutput
Following are the state meaning and timing comments for the ABB output signal.
State Meaning
Timing Comments AssertionÑOccurs the cycle after a qualiÞed BG is accepted by
MOTOROLA
NegationÑMay occur whenever the MPC8260 must be prevented
from using the address bus. The MPC8260 may still assume address
bus ownership on the cycle BG is negated if it was asserted the
previous cycle with other bus grant qualiÞcations.
AssertedÑIndicates that the external device may, with the proper
qualiÞcation, begin a bus transaction and assume ownership of the
address bus. A qualiÞed bus grant is generally determined from the
bus state as follows: QBG = BG ¥ ÂABB ¥ ÂARTRY where ARTRY
is asserted only during the cycle after AACK. Note that the assertion
of BR is not required for a qualiÞed bus grant (for bus parking).
NegatedÑIndicates that the external device is not granted next
address ownership.
assumed address bus ownership, it does not begin checking for BG
again until the cycle after AACK.
NegationÑMay occur when an external device must be kept from
using the address bus. The external device may still assume address
bus ownership on the cycle that BG is negated if it was asserted the
previous cycle with other bus grant qualiÞcations.
AssertedÑIndicates that the MPC8260 is the current address bus
master. The MPC8260 may not assume address bus ownership in
case a bus request is internally cancelled by the cycle a qualiÞed BG
would have been recognized.
NegatedÑIndicates that MPC8260 is not the current address bus
master.
MPC8260 and remains asserted for the duration of the address
tenure.
Turn-Off SequencingÑNegates for a fraction of a bus cycle (1/2
minimum, depends on clock mode) starting the cycle following the
assertion of AACK. It then goes to the high impedance state.
Chapter 7. 60x Signals
Part III. The Hardware Interface
7-5
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