Interrupt Vector Generation And Calculation - Motorola MPC8260 PowerQUICC II User Manual

Part II. ConÞguration and Reset
SCCE
Event
Bit
SCCM
Mask
Bit

4.2.4 Interrupt Vector Generation and Calculation

Pending unmasked interrupts are presented to the core in order of priority. The interrupt
vector that allows the core to locate the interrupt service routine is made available to the
core by reading SIVEC. The interrupt controller passes an interrupt vector corresponding
to the highest-priority, unmasked, pending interrupt. Table 4-3 lists encodings for the six
low-order bits of the interrupt vector.
Interrupt Number
0
1
2
3
4
5
4-14
13 Input (or
13 Event Bits)
Mask
Bit
Figure 4-9. Interrupt Request Masking
Table 4-3. Encoding the Interrupt Vector
Interrupt Source Description
Error (No interrupt)
2
I C
SPI
RISC Timers
SMC1
SMC2
MPC8260 PowerQUICC II UserÕs Manual
SIPNR
(Other Unmasked Requests)
SIMR
Interrupt Vector
0b00_0000
0b00_0001
0b00_0010
0b00_0011
0b00_0100
0b00_0101
Request to
the core
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