The Spi As A Slave Device; The Spi In Multimaster Operation - Motorola MPC8260 PowerQUICC II User Manual

Part IV. Communications Processor Module
To start exchanging data, the core writes the data to be sent into a buffer, conÞgures a TxBD
with TxBD[R] set, and conÞgures one or more RxBDs. The core then sets SPCOM[STR]
in the SPI command register to start sending data, which starts once the SDMA channel
loads the Tx FIFO with data.
The SPI then generates programmable clock pulses on SPICLK for each character and
simultaneously shifts Tx data out on SPIMOSI and Rx data in on SPIMISO. Received data
is written into a Rx buffer using the next available RxBD. The SPI keeps sending and
receiving characters until the whole buffer is sent or an error occurs. The CP then clears
TxBD[R] and RxBD[E] and issues a maskable interrupt to the interrupt controller in the
SIU.
When multiple TxBDs are ready, TxBD[L] determines whether the SPI keeps transmitting
without SPCOM[STR] being set again. If the current TxBD[L] is cleared, the next TxBD
is processed after data from the current buffer is sent. Typically there is no delay on
SPIMOSI between buffers. If the current TxBD[L] is set, sending stops after the current
buffer is sent. In addition, the RxBD is closed after transmission stops, even if the Rx buffer
is not full; therefore, Rx buffers need not be the same length as Tx buffers.

33.3.2 The SPI as a Slave Device

In slave mode, the SPI receives messages from an SPI master and sends a simultaneous
reply. The slaveÕs SPISEL must be asserted before Rx clocks are recognized; once SPISEL
is asserted, SPICLK becomes an input from the master to the slave. SPICLK can be any
frequency from DC to BRGCLK/2 (12.5 MHz for a 25-MHz system).
To prepare for data transfers, the slaveÕs core writes data to be sent into a buffer, conÞgures
a TxBD with TxBD[R] set, and conÞgures one or more RxBDs. The core then sets
SPCOM[STR] to activate the SPI. Once SPISEL is asserted, the slave shifts data out from
SPIMISO and in through SPIMOSI. A maskable interrupt is issued when a full buffer
Þnishes receiving and sending or after an error. The SPI uses successive RxBDs in the table
to continue reception until it runs out of Rx buffers or SPISEL is negated.
Transmission continues until no more data is available or SPISEL is negated. If it is negated
before all data is sent, it stops but the TxBD stays open. Transmission continues once
SPISEL is reasserted and SPICLK begins toggling. After the characters in the buffer are
sent, the SPI sends ones as long as SPISEL remains asserted.

33.3.3 The SPI in Multimaster Operation

The SPI can operate in a multimaster environment in which SPI devices are connected to
the same bus. In this conÞguration, the SPIMOSI, SPIMISO, and SPICLK signals of all
SPIs are shared; the SPISEL inputs are connected separately, as shown in Figure 33-3. Only
one SPI device can act as master at a timeÑall others must be slaves. When an SPI is
conÞgured as a master and its SPISEL input is asserted, a multimaster error occurs because
more than one SPI device is a bus master. The SPI sets SPIE[MME] in the SPI event register
and a maskable interrupt is issued to the core. It also disables SPI operation and the output
33-4 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA