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Paragraph
Number
33.4.3
SPI Command Register (SPCOM) .................................................................33-9
33.5
SPI Parameter RAM .........................................................................................33-10
33.5.1
Receive/Transmit Function Code Registers (RFCR/TFCR) ........................33-12
33.6
SPI Commands .................................................................................................33-12
33.7
The SPI Buffer Descriptor (BD) Table.............................................................33-13
33.7.1
SPI Buffer Descriptors (BDs).......................................................................33-13
33.7.1.1
SPI Receive BD (RxBD) ..........................................................................33-14
33.7.1.2
SPI Transmit BD (TxBD).........................................................................33-15
33.8
SPI Master Programming Example ..................................................................33-16
33.9
SPI Slave Programming Example ....................................................................33-17
33.10
Handling Interrupts in the SPI ..........................................................................33-18
34.1
Features...............................................................................................................34-2
2
34.2
I
C Controller Clocking and Signal Functions...................................................34-2
2
34.3
I
C Controller Transfers.....................................................................................34-3
2
34.3.1
I
C Master Write (Slave Read) ......................................................................34-4
2
34.3.2
I
C Loopback Testing ....................................................................................34-4
2
34.3.3
I
C Master Read (Slave Write) ......................................................................34-4
2
34.3.4
I
C Multi-Master Considerations ...................................................................34-5
2
34.4
I
C Registers.......................................................................................................34-6
2
34.4.1
I
C Mode Register (I2MOD) .........................................................................34-6
2
34.4.2
I
C Address Register (I2ADD) ......................................................................34-7
2
34.4.3
I
C Baud Rate Generator Register (I2BRG) ..................................................34-7
2
34.4.4
I
C Event/Mask Registers (I2CER/I2CMR) ..................................................34-8
2
34.4.5
I
C Command Register (I2COM) ..................................................................34-8
2
34.5
I
C Parameter RAM ...........................................................................................34-9
2
34.6
I
C Commands .................................................................................................34-11
2
34.7
2
34.7.1
I
C Buffer Descriptors (BDs).......................................................................34-12
34.7.1.1
I
34.7.1.2
I
35.1
Features...............................................................................................................35-1
35.2
Port Registers......................................................................................................35-2
35.2.1
Port Open-Drain Registers (PODRAÐPODRD).............................................35-2
35.2.2
Port Data Registers (PDATAÐPDATD).........................................................35-2
xxx
CONTENTS
2
I
C Buffer Descriptor (BD) Table.............................................................34-12
2
C Receive Buffer Descriptor (RxBD) ...................................................34-13
2
C Transmit Buffer Descriptor (TxBD)..................................................34-14
MPC8260 PowerQUICC II UserÕs Manual
Title
Chapter 34
C Controller
Chapter 35
Page
Number
MOTOROLA
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