Scc Hdlc Status Register (Sccs); Scc Hdlc Programming Examples - Motorola MPC8260 PowerQUICC II User Manual

Part IV. Communications Processor Module

21.12 SCC HDLC Status Register (SCCS)

The SCC status register (SCCS), shown in Figure 21-9, permits monitoring of real-time
status conditions on RXD. The real-time status of CTS and CD are part of the port C
parallel I/O.
Bit 0
Field
Reset
R/W
Addr 0x11A17 (SCCS1); 0x11A37 (SCCS2); 0x11A57 (SCCS3); 0x11A77 (SCCS4)
Figure 21-9. SCC HDLC Status Register (SCCS)
Table 21-10 describes HDLC SCCS Þelds.
Bits Name
0Ð4 Ñ Reserved, should be cleared.
5 FG Flags. The line is checked after the data has been decoded by the DPLL.
0 HDLC ßags are not being received. The most recently received 8 bits are examined every bit time to
see if a ßag is present.
1 HDLC ßags are being received. FG is set as soon as an HDLC ßag (0x7E) is received on the line.
Once it is set, it remains set at least 8 bit times and the next eight received bits are examined. If
another ßag occurs, FG stays set for at least another eight bits. If not, it is cleared and the search
begins again.
6 CS Carrier sense (DPLL). Shows the real-time carrier sense of the line as determined by the DPLL.
0 The DPLL does not sense a carrier.
1 The DPLL senses a carrier.
7 ID Idle status.
0 The line is busy.
1 Set when RXD is a logic 1 (idle) for 15 or more consecutive bit times. It is cleared after a single logic
0 is received.

21.13 SCC HDLC Programming Examples

The following sections show examples for programming SCCs in HDLC mode. The Þrst
example uses an external clock. The second example implements Manchester encoding.
21-14
1 2
Ñ
Table 21-10. HDLC SCCS Field Descriptions
MPC8260 PowerQUICC II UserÕs Manual
3 4 5
FG
0000_0000
R
Description
6 7
CS ID
MOTOROLA