Motorola MPC8260 PowerQUICC II User Manual page 126

Part I. Overview
Internal
Abbreviation
Address
10D92 TMR2
10D94 TRR1
10D96 TRR2
10D98 TCR1
10D9A TCR2
10D9C TCN1
10D9E TCN2
10DA0 TMR3
10DA2 TMR4
10DA4 TRR3
10DA6 TRR4
10DA8 TCR3
10DAA TCR4
10DAC TCN3
10DAE TCN4
10DB0 TER1
10DB2 TER2
10DB4 TER3
10DB6 TER4
10D74Ð11017 Reserved
11018 SDSR
11019 Reserved
1101C SDMR
1101D Reserved
11020 IDSR1
11021 Reserved
11024 IDMR1
11025 Reserved
11028 IDSR2
3-6
Table 3-1. Internal Memory Map (Continued)
Name
Timer 2 mode register
Timer 1 reference register
Timer 2 reference register
Timer 1 capture register
Timer 2 capture register
Timer 1 counter
Timer 2 counter
Timer 3 mode register
Timer 4 mode register
Timer 3 reference register
Timer 4 reference register
Timer 3 capture register
Timer 4 capture register
Timer 3 counter
Timer 4 counter
Timer 1 event register
Timer 2 event register
Timer 3 event register
Timer 4 event register
Ñ
SDMAÐGeneral
SDMA status register
Ñ
SDMA mask register
Ñ
IDMA 1 event register
Ñ
IDMA 1 mask register
Ñ
IDMA 2 event register
MPC8260 PowerQUICC II UserÕs Manual
Size
16 bits
16 bits
16 bits
16 bits
16 bits
16 bits
16 bits
16 bits
16 bits
16 bits
16 bits
16 bits
16 bits
16 bits
16 bits
16 bits
16 bits
16 bits
16 bits
670 bytes
8 bits
24 bits
8 bits
24 bits
IDMA
8 bits
24 bits
8 bits
24 bits
8 bits
Section/Page Number
17.2.3/17-6
17.2.4/17-7
17.2.4/17-7
17.2.5/17-8
17.2.5/17-8
17.2.6/17-8
17.2.6/17-8
17.2.3/17-6
17.2.3/17-6
17.2.4/17-7
17.2.4/17-7
17.2.5/17-8
17.2.5/17-8
17.2.6/17-8
17.2.6/17-8
17.2.7/17-8
17.2.7/17-8
17.2.7/17-8
17.2.7/17-8
Ñ
18.2.1/18-3
Ñ
18.2.2/18-4
Ñ
18.8.4/18-22
Ñ
18.8.4/18-22
Ñ
18.8.4/18-22
MOTOROLA