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26.4.11 SMC Transparent NMSI Programming Example
The following example initializes the SMC1 transparent channel over its own set of signals.
The CLK9 signal supplies the transmit and receive clocks; the SMSYNx signal is used for
synchronization. (The SMC UART programming example uses a BRG conÞguration; see
Section 26.3.12, ÒSMC UART Controller Programming Example.Ó)
1. ConÞgure the port D pins to enable SMTXD1, SMRXD1, and SMSYN1. Set
PPARD[7,8,9] and PDIRD[9]. Clear PDIRD[7,8] and PSORD[7,8,9].
2. ConÞgure the port C pins to enable CLK9. Set PPARC[23]. Clear PDIRC[23] and
PSORC[23].
3. Connect CLK9 to SMC1 using the CPM mux. Clear CMXSMR[SMC1] and
program CMXSMR[SMC1CS] to 0b11.
4. In address 0x87FC, assign a pointer to the SMC1 parameter RAM.
5. Write RBASE and TBASE in the SMC parameter RAM to point to the RxBD and
TxBD in the dual-port RAM. Assuming one RxBD at the beginning of the dual-port
RAM followed by one TxBD, write RBASE with 0x0000 and TBASE with 0x0008.
6. Write 0x1D01_0000 to CPCR to execute the
command.
7. Write RFCR and TFCR with 0x10 for normal operation.
8. Write MRBLR with the maximum bytes per receive buffer. Assuming 16 bytes
MRBLR = 0x0010.
9. Initialize the RxBD assuming the buffer is at 0x0000_1000 in main memory. Write
0xB000 to RxBD[Status and Control], 0x0000 to RxBD[Data Length] (optional),
and 0x0000_1000 to RxBD[Buffer Pointer].
10. Initialize the TxBD assuming the Tx buffer is at 0x0000_2000 in main memory and
contains Þve 8-bit characters. Write 0xB800 to TxBD[Status and Control], 0x0005
to TxBD[Data Length], and 0x0000_2000 to TxBD[Buffer Pointer].
11. Write 0xFF to SMCE1 to clear any previous events.
12. Write 0x13 to SMCM1 to enable all possible SMC1 interrupts.
13. Write 0x0000_1000 to the SIU interrupt mask register low (SIMR_L) so the SMC1
can generate a system interrupt. Write 0xFFFF_FFFF to the SIU interrupt pending
register low (SIPNR_L) to clear events.
14. Write 0x3830 to the SMCMR to conÞgure 8-bit characters, unreversed data, and
normal operation (not loopback). The transmitter and receiver are not enabled yet.
15. Write 0x3833 to the SMCMR to enable the SMC transmitter and receiver. This
additional write ensures that TEN and REN are enabled last.
After 5 bytes are sent, the TxBD is closed; after 16 bytes are received the receive buffer is
closed. Any data received after 16 bytes causes a busy (out-of-buffers) condition since only
one RxBD is prepared.
MOTOROLA
Chapter 26. Serial Management Controllers (SMCs)
Part IV. Communications Processor Module
INIT RX AND TX PARAMETERS
26-29
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