Motorola MPC8260 PowerQUICC II User Manual page 972

Part IV. Communications Processor Module
Table 35-7. Port C Dedicated Pin Assignment (PPARC = 1) (Continued)
PIN
PDIRC = 1 (Output)
PC10 FCC1: TxD[2]
UTOPIA 16
PC9 FCC1: TxD[1]
UTOPIA 16
PC8 FCC1: TxD[0]
UTOPIA 16
PC7 TDM_C1: L1RQ
PC6 TDM_C1: L1CLKO
PC5 FCC2: TxClav
UTOPIA, slave
PC4 FCC2: RxEnb
UTOPIA, master
PC3 FCC2: TxD[2]
UTOPIA 8
PC2 FCC2: TxD[3]
UTOPIA 8
PC1 BRG6: BRGO
PC0 BRG7: BRGO
1
Available only when the primary option for this function is not used.
2
MPHY Address pins 3,4 (master mode) can come from FCC2, depending on CMXUAR programming. (See
Section 15.4.1, ÒCMX UTOPIA Address Register (CMXUAR).Ó).
35-16
PSORC = 0
Default
PDIRC = 0 (Input)
Input
SCC3: CD GND
SCC3: RENA
Ethernet
SCC4: CTS by PC3
SCC4: CLSN
Ethernet
(primary option)
SCC4: CD GND
SCC4: RENA
Ethernet
FCC1: CTS GND
FCC1: CD GND
FCC2: TxClav GND
UTOPIA, master
FCC2: RxEnb GND
UTOPIA, slave
FCC3: CTS GND
FCC3: CD GND
IDMA2: DREQ GND
IDMA1: DREQ GND
MPC8260 PowerQUICC II UserÕs Manual
Pin Function
PDIRC = 1 (Output)
SI1: L1ST4
strobe
SI2: L1ST1
strobe
SI2: L1ST2
Strobe
FCC1: TxAddr[2]
MPHY master,
multiplexed: polling
FCC1: RxAddr[2]
MPHY, master,
multiplexed polling
SI2: L1ST3
Strobe
SI2: L1ST4
Strobe
IDMA2: DACK
TDM_A2: L1RQ
TDM_A2: L1CLKO
PSORC = 1
PDIRC = 0 (Input or Default
Inout if SpeciÞed) Input
1
FCC2: RxD[3] GND
UTOPIA
(secondary option)
TDM_A2: L1TSYNC/ GND
1
GRANT
(secondary option)
1
SCC3: CTS GND
(secondary option)
2
FCC1: TxAddr[2] GND
MPHY, slave,
multiplexed polling
2
FCC1: TxClav1
MPHY, master, direct
polling
FCC2: TxAddr[2]
MPHY, slave,
multiplexed polling
2
FCC1: RxAddr[2] GND
MPHY, slave,
multiplexed polling)
2
FCC1: RxClav1
MPHY, master, direct
polling
FCC2: RxAddr[2]
MPHY, slave,
multiplexed polling
FCC2: CTS GND
FCC2: CD GND
1
SCC4: CTS GND
(secondary option)
IDMA2: DONE
Inout
1
SMC2: SMSYN GND
(secondary option)
MOTOROLA
V
DD