Bus-Assigned Sdram Refresh Timer (Psrt) - Motorola MPC8260 PowerQUICC II User Manual

Table 10-13 describes LURT Þelds.
Table 10-13. Local Bus-Assigned UPM Refresh Timer (LURT)
Bits Name
0Ð7 LURT Refresh timer period. Determines the timer period according to the following equation:
TimerPeriod
This timer generates a refresh request for all valid banks that selected a UPM machine assigned to
the local bus (MxMR[BSEL] =1) and is refresh-enabled (MxMR[RFEN] =1). Each time the timer
expires, a qualiÞed bank generates a refresh request using the selected UPM. The qualiÞed banks
are rotating their requests.
Example: For a 25-MHz system clock and a required service rate of 15.6 µs, given
MPTPR[PTP] = 32, the LURT value should be 12 decimal. 12/(25 MHz/32) = 15.36 µs, which is less
than the required service period of 15.6 µs.
10.3.10 60x Bus-Assigned SDRAM Refresh Timer (PSRT)
The 60x bus assigned SDRAM refresh timer register (PSRT) is shown in Figure 10-16.
Bit 0
Field
Reset
R/W
Addr
Figure 10-16. 60x Bus-Assigned SDRAM Refresh Timer (PSRT)
Table 10-14 describes PSRT Þelds.
Table 10-14. 60x Bus-Assigned SDRAM Refresh Timer (PSRT)
Bits Name
0Ð7 PSRT Refresh timer period. Determines the timer period according to the following equation:
TimerPeriod
This timer generates refresh requests for all valid banks that selected a SDRAM machine assigned to
the 60x bus and is refresh-enabled (PSDMR[RFEN] = 1). Each time the timer expires, all banks that
qualify generate a bank staggering auto refresh request using the SDRAM machine. See
Section 10.4.10, ÒSDRAM Refresh.Ó
Example: For a 25-MHz system clock and a required service rate of 15.6 µs, given MPTPR[PTP] = 32,
the PSRT value should be 12 decimal. 12/(25 MHz/32) = 15.36 µs, which is less than the required
service period of 15.6 µs.
MOTOROLA
æ LURT ö
= ---------------- -
è ø
F
MPTC
1 2
æ ö
PSRT
---------------- -
=
è ø
F
MPTC
Chapter 10. Memory Controller
Part III. The Hardware Interface
Description
3 4
PSRT
0000_0000
R/W
0x1019C
Description
5 6 7
10-31