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REFRESH CONTROL UNIT
Register Name:
Register Mnemonic:
Register Function:
15
R
E
N
Bit
Mnemonic
REN
Refresh
Control Unit
Enable
RC8:0
Refresh
Counter
NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written
to a logic zero to ensure compatibility with future Intel products.
7.7.2.4
Refresh Address Register
The Refresh Address Register (Figure 7-9) contains address bits RA12:1, which will appear on
the bus as A12:1 on the next refresh bus cycle. Bit 0 is fixed as a one in the register and in all
refresh addresses.
7-10
Refresh Control Register
RFCON
Controls Refresh Unit operation.
R
C
8
Reset
Bit Name
State
0
000H
Figure 7-8. Refresh Control Register
R
R
R
R
C
C
C
C
7
6
5
4
Function
Setting REN enables the Refresh Unit. Clearing
REN disables the Refresh Unit.
These bits contain the present value of the
down-counter that triggers refresh requests.
The user cannot program these bits.
0
R
R
R
R
C
C
C
C
3
2
1
0
A1311-0A
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