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BUS INTERFACE UNIT
CLKOUT
NMI/NTx
ALE
S2:0
AD15:0
[AD7:0]
[A15:8]
A19:16
BHE
RFSH
NOTE:
1. For NMI, delay = 4 1/2 clocks. For INTx, delay = 7 1/2 clocks (min).
2. If previous bus cycle was a read, bus will float. If previous bus cycle was
a write, bus will drive data value.
3. Previous bus cycle value.
4. If previous bus cycle was a refresh or DMA bus cycle, value will be
8H (A19 = 1), otherwise value will be 0.
3.6
SYSTEM DESIGN ALTERNATIVES
Most system designs require no signals other than those already provided by the BIU. However,
heavily loaded bus conditions, slow memory or peripheral device performance and off-board de-
vice interfaces may not be supported directly without modifying the BIU interface. The following
sections deal with topics to enhance or modify the operation of the BIU.
3-36
Note 1
Figure 3-30. Exiting HALT (Active/Idle Mode)
Note 2
Note 3
Note 4
Note 3
Valid
Addr
Address
A1093-0A
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