Module Integration: The 80C186Ec Interrupt Control Unit - Intel 80C188EC User Manual

INTERRUPT CONTROL UNIT
8.5

MODULE INTEGRATION: THE 80C186EC INTERRUPT CONTROL UNIT

The 80C186EC/C188EC Interrupt Control Unit uses two 8259A modules with additional support
circuitry. This section describes the integration of the two 8259A modules and the programming
of the Interrupt Control Unit.
8.5.1 Internal Interrupt Sources
The 80C186/C188EC has a total of eleven internal interrupt requests from the on-chip peripher-
als.
•
Timer 0 Maximum Count (TMI0)
•
Timer 1 Maximum Count (TMI1)
•
Timer 2 Maximum Count (TMI2)
•
DMA Channel 0 Terminal Count (DMAI0) *
•
DMA Channel 1 Terminal Count (DMAI1) *
•
DMA Channel 2 Terminal Count (DMAI2)
•
DMA Channel 3 Terminal Count (DMAI3)
•
Serial Channel 0 Receive Complete (RXI0)
•
Serial Channel 0 Transmit Complete (TXI0)
•
Serial Channel 1 Receive Complete (RXI1) *
•
Serial Channel 1 Transmit Complete (TXI1) *
* These sources are indirectly supported. See "Indirectly Supported Internal Interrupt
Sources" on page 8-38.
Internally, the request from each of these sources is an active-high pulse that is valid for one-half
clock cycle. The Interrupt Request Latch Registers convert the pulsed request into a valid level
for the 8259A modules (see Figure 8-21). The Interrupt Request Latch Registers also add inter-
rupt handler testing capability to the 80C186EC/C188EC.
There are three Interrupt Request Registers: one for the Timer/Counter Unit (TIMIRL), one for
the DMA Unit (DMAIRL) and one for the Serial Communication Unit (SCUIRL).
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