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10. On the second falling edge of INTA, the slave 8259A module drives the interrupt type
corresponding to IR2 on the data bus. The CAS2:0 lines return to their inactive low state
and the slave 8259A module floats its data bus when INTA goes high. The interrupt
request signal from the master 8259A module to the CPU goes inactive (low). The master
8259A module does not drive the data bus during a slave acknowledge.
11. The CPU executes the interrupt processing sequence and begins to execute the interrupt
handler for a slave IR2.
12. The slave IR2 handler completes execution. The final instructions of the handler issue an
End-of-Interrupt (EOI) command to the master 8259A module and a second EOI
command to the slave 8259A module. This completes the servicing of slave IR2.
8.3.6.3
Master Cascade Configuration
The Master Cascade Configuration Register includes one bit for each of the eight interrupt re-
quest lines on the master 8259A module. Setting a bit for an IR line informs the master 8259A
module that a slave 8259A module is connected to that IR line. The master uses the Master Cas-
cade Configuration bits during an interrupt acknowledge cycle to determine whether the CAS
lines should be active. The CAS lines are active only when a cascaded input is being acknowl-
edged; the value on the CAS bus is equal to the line number of the cascaded interrupt request. For
example, if the master is acknowledging an interrupt from a slave cascaded on line IR4, then the
CAS2:0 bus is driving 100 binary (4 decimal).
8.3.6.4
Slave ID
The slave ID must always be programmed equal to the master IR line to which the slave is con-
nected. For example, if a slave's interrupt request output is connected to the master's IR6 line,
then that slave must be programmed for a slave ID of six. A slave 8259A module responds to an
INTA signal (and deposits a vector on the bus) only if its slave ID and the CAS2:0 address match.
Special precautions must be taken when connecting a slave to IR0 of a master 8259A module. A
slave programmed for an ID of zero is active both for interrupts that it has requested and for un-
cascaded master interrupts (uncascaded interrupts leave the CAS lines inactive low). If this situ-
ation occurs, there will be contention on the data bus as both the master and the slave attempt to
drive the interrupt type on the data bus. Never cascade a slave 8259A module to IR0 of a master
module unless IR0 is the last available uncascaded input (i.e., the system is fully cascaded with
eight slave 8259A modules).
8.3.6.5
Issuing EOI Commands in a Cascaded System
Interrupt handlers for slave interrupts must issue two EOI commands: one for the master and one
for the slave. The master EOI must be sent first, followed by the slave EOI.
INTERRUPT CONTROL UNIT
8-17
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