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PERIPHERAL CONTROL BLOCK
Register Name:
Register Mnemonic:
Register Function:
15
E
T
Bit
Mnemonic
ET
Escape Trap
MEM
Memory I/O
R19:8
PCB Base
Address
Upper Bits
NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written
to a logic zero to ensure compatibility with future Intel products.
PCB
Function
Offset
00H
MPICP0
02H
MPICP1
4-2
PCB Relocation Register
RELREG
Relocates the PCB within memory or I/O space.
M
R
R
R
R
E
1
1
1
1
M
9
8
7
6
Reset
Bit Name
State
0
The ET bit controls access to the math copro-
cessor. If ET is set, the CPU will trap (resulting in
a Type 7 interrupt) when an ESC instruction is
executed.
NOTE: The 8-bit bus version of the device
automatically traps an ESC opcode to the Type 7
interrupt, regardless of the state of the ET bit.
0
The MEM bit specifies the PCB location. Set
MEM to locate the PCB in memory space, or
clear it to locate the PCB in I/O space.
0FFH
R19:8 define the upper address bits of the PCB
base address. All lower bits are zero. R19:16 are
ignored when the PCB is mapped to I/O space.
Figure 4-1. PCB Relocation Register
Table 4-1. Peripheral Control Block
PCB
Function
Offset
40H
T2CNT
42H
T2CMPA
R
R
R
R
R
1
1
1
1
1
5
4
3
2
1
Function
PCB
Function
Offset
80H
GCS0ST
82H
GCS0SP
0
R
R
R
1
9
8
0
A1263-0A
PCB
Function
Offset
C0H
D0SRCL
C2H
D0SRCH
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