Masking Interrupts - Intel 80C188EC User Manual

INTERRUPT CONTROL UNIT
Use of Automatic EOI Mode precludes a fully nested interrupt structure. When Automatic EIO
Mode is selected, the In-Service bit is cleared before the handler begins execution. As soon as the
In-Service bit is cleared, any unmasked source (of any priority) can interrupt the handler.
Automatic EOI Mode can be used only in a master 8259A in a cascaded system. Using Automatic
EOI Mode for a slave in a cascaded system will lead to system malfunction.
8.3.5

Masking Interrupts

During program execution, the CPU may wish to ignore certain interrupts while enabling others.
The Interrupt Mask Register is used to selectively enable and disable each IR line. The masking
operation physically takes place after the Interrupt Request Register. A masked interrupt still sets
its corresponding Interrupt Request Register bit.
External maskable interrupts can be globally enabled and disabled within the CPU itself. The In-
terrupt Enable Flag in the Processor Status Word controls the global masking of external inter-
rupts. (See Chapter 2, "Overview of the 80C186 Family Architecture," for more information
about the Interrupt Enable Flag.)
8.3.6 Cascading 8259As
The 8259A module includes the capability to cascade up to 8 slave interrupt controllers to a single
master module. In a fully cascaded system, the interrupt request capability is extended to 64 lev-
els. (The 80C186EC/C188EC Interrupt Control Unit uses a cascaded configuration.)
8.3.6.1 Master/Slave Connection
Figure 8-9 shows a typical master/slave connection. In a cascade configuration, each slave 8259A
module connects its interrupt output to one of the master 8259A module's interrupt request in-
puts. The master controls the actions of the slaves through the Cascade Bus (CAS2:0). Each slave
device in a system has a unique Slave ID, which must be programmed to the same numerical val-
ue as the master IR line to which it is connected. During an interrupt acknowledge cycle, the mas-
ter 8259A drives CAS2:0 lines with the Slave ID of the slave that is being acknowledged. The
Cascade Bus lines are inactive low and are active only during interrupt acknowledge cycles.
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