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OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE
2.3.1.1
Non-Maskable Interrupts
The Non-Maskable Interrupt (NMI) is the highest priority interrupt. It is usually reserved for a
catastrophic event such as impending power failure. An NMI cannot be prevented (or masked)
by software. When the NMI input is asserted, the interrupt processing sequence begins after ex-
ecution of the current instruction completes (see "Interrupt Latency" on page 2-44). The CPU au-
tomatically generates a type 2 interrupt vector.
The NMI input is asynchronous. Setup and hold times are given only to guarantee recognition on
a specific clock edge. To be recognized, NMI must be asserted for at least one CLKOUT period
and meet the correct setup and hold times. NMI is edge-triggered and level-latched. Multiple
NMI requests cause multiple NMI service routines to be executed. NMI can be nested in this man-
ner an infinite number of times.
2.3.1.2
Maskable Interrupts
Maskable interrupts are the most common way to service external hardware interrupts. Software
can globally enable or disable maskable interrupts. This is done by setting or clearing the Inter-
rupt Enable bit in the Processor Status Word.
The Interrupt Control Unit processes the multiple sources of maskable interrupts and presents
them to the core via a single maskable interrupt input. The Interrupt Control Unit provides the
interrupt vector type to the 80C186 Modular Core. The Interrupt Control Unit differs among
members of the 80C186 Modular Core family; see Chapter 7, "Interrupt Control Unit," for infor-
mation.
2.3.1.3
Exceptions
Exceptions occur when an unusual condition prevents further instruction processing until the ex-
ception is corrected. The CPU handles software interrupts and exceptions in the same way. The
interrupt type for an exception is either predefined or supplied by the instruction.
Exceptions are classified as either faults or traps, depending on when the exception is detected
and whether the instruction that caused the exception can be restarted. Faults are detected and ser-
viced before the faulting instruction can be executed. The return address pushed onto the stack
in the interrupt processing instruction points to the beginning of the faulting instruction. This al-
lows the instruction to be restarted. Traps are detected and serviced immediately after the instruc-
tion that caused the trap. The return address pushed onto the stack during the interrupt processing
points to the instruction following the trapping instruction.
Divide Error — Type 0
A Divide Error trap is invoked when the quotient of an attempted division exceeds the maximum
value of the destination. A divide-by-zero is a common example.
2-42
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