Icw3: Cascaded Pins/Slave Address - Intel 80C188EC User Manual

INTERRUPT CONTROL UNIT
8.4.3.4

ICW3: Cascaded Pins/Slave Address

The function of ICW3 differs between 8259A modules configured as masters and those config-
ured as slaves. ICW3 is accepted by the 8259A module only if it has been programmed for cas-
cade mode.
In a master 8259A module, ICW3 is the Master Cascade Configuration Register (Figure 8-14).
Each bit in the Master Cascade Configuration Register corresponds to an interrupt request line.
Setting a bit in this register informs the master 8259A module that a slave 8259A module is con-
nected to the corresponding input. For example, if a slave is connected to IR3 of the master, the
S3 bit in the master must be set.
In a slave 8259A module, ICW3 is the Slave ID Register (Figure 8-15). The programmed ID of
a slave must match the IR on the master to which the slave is connected. For example, if a slave
is connected to IR7 of the master 8259A module, then the slave's ID must be programmed to sev-
en.
8.4.3.5 ICW4: Special Fully Nested Mode, EOI Mode, Factory Test Modes
The bit positions and definitions for ICW4 are shown in Figure 8-16. The SFNM bit is used to
select Special Fully Nested Mode, and the AEOI bit is used to select the Automatic EOI Mode.
These modes can be used only in the master of a cascaded system.
The FT2:0 bits are used to select test modes during factory test. The 8259A test modes redefine
the 80C186EC/C188EC pinout to facilitate device testing.
The FT2:0 bits must be programmed with the values shown in Figure 8-16. Failure
CAUTION:
to follow this guideline will result in system failure and possible damage to the
80C186EC/C188EC system.
The remaining bits in the ICW4 register must be programmed with the bit values specified in Fig-
ure 8-16.
8-26