Exiting Halt - Intel 80C188EC User Manual

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BUS INTERFACE UNIT

NOTE: Drives previous bus cycle value

Figure 3-28. Returning to HALT After a DMA Bus Cycle

Exiting HALT

Any NMI or maskable interrupt forces the BIU to exit the HALT bus state (in any power man-

agement mode). The first bus operations to occur after exiting HALT are read cycles to reload the

CS:IP registers. Figure 3-29 and Figure 3-30 show how the HALT bus state is exited when an

NMI or INTn occurs.

T1 T2 T3 T4 T1 T2 T3

Valid Status

Valid Status