Enabling And Disabling Chip-Selects - Intel 80C188EC User Manual

In the previous equations, a stop value of 1023 (03FFH) results in a physical ending address of
0FFBFFH (memory) or 0FFBFH (I/O). These addresses do not represent the top of the memory
or I/O address space. To have a chip-select enabled to the end of the physical address space, the
ISTOP control bit must be set. The ISTOP control bit overrides the stop address comparator out-
put (see Figure 6-2 on page 6-3).
6.4.4

Enabling and Disabling Chip-Selects

The ability to enable or disable a chip-select is important when multiple memory devices share
(or can share) the same physical address space. Examples of where two or more devices would
occupy the same address space include shadowed memory, bank switching and paging.
The STOP register holds the CSEN control bit, which determines whether the chip-select should
go active. A chip-select never goes active if its CSEN control bit is cleared.
Chip-selects can be disabled by programming the stop address value less than the start address
value or by programming the start address value greater than the stop address value. However,
the ISTOP control bit cannot be set when chip-selects are disabled in this manner.
6.4.5 Bus Wait State and Ready Control
Normally, the bus ready input must be inactive at the appropriate time to insert wait states into
the bus cycle. The Chip-Select Unit can ignore the state of the bus ready input to extend and com-
plete the bus cycle automatically. Most memory and peripheral devices operate properly using
fifteen or fewer wait states. However, accessing such devices as a dual-port memory, an expan-
sion bus interface, a system bus interface or remote peripheral devices can require more than fif-
teen wait states to complete a bus cycle.
The START register holds a four-bit value (WS3:0) that defines the number of wait states to in-
sert into the bus cycle. Figure 6-7 shows a simplified logic diagram of the wait state and ready
control functions.
CHIP-SELECT UNIT
6-11