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Register Name:
Register Mnemonic:
Register Function:
15
C
C
C
S
S
S
9
8
7
Bit
Mnemonic
MEM
Bus Cycle
Selector
RDY
Bus Ready
Enable
NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written
to a logic zero to ensure compatibility with future Intel products. The reset state of
CSEN and ISTOP is '1' for the UCSSP register.
Figure 6-6. STOP Register Definition (Continued)
The correct sequence to program a non-enabled chip-select is as follows. (If the chip-select is al-
ready enabled, either reverse the sequence or disable the chip-select before reprogramming it.)
1.
Program the START register
2.
Program the STOP register
Chip-Select Stop Register
UCSSP, LCSSP, GCSxSP (x=0-7)
Defines chip-select stop address and other control
functions.
C
C
C
C
C
S
S
S
S
S
6
5
4
3
2
Reset
Bit Name
State
1
1
C
C
S
S
1
0
Function
When MEM is set, the chip-select goes active
for memory bus cycles. Clearing MEM activates
the chip-select for I/O bus cycles.
MEM defines which address bits are used by
the start and stop address comparators. When
MEM is cleared, address bits A15:6 are routed
to the comparators. When MEM is set, address
bits A19:10 are routed to the comparators.
Setting RDY requires that bus ready be active
to complete a bus cycle. Bus ready is ignored
when RDY is cleared. RDY must be set to
extend wait states beyond the number
determined by WS3:0.
CHIP-SELECT UNIT
0
C
I
M
R
S
S
E
D
E
T
M
Y
N
O
P
A1164-0A
6-9
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