Watchdog Timer Registers - Intel 80C188EC User Manual

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WATCHDOG TIMER UNIT
wdt_data
segment
wdt_off
DB
wdt_data
ends
pcb_image
segment;image of PCB
WDTDIS
EQU
WDTDIS
DW
pcb_image
ends
wdt_code
segment
assume cs:wdt_code
mov
mov
mov
mov
mov
mov
cld
mov
lock rep
movsb
wdt_code
ends
Example 12-4. Disabling the Watchdog Timer (Peripheral Control Block in Memory Space)

12.5 WATCHDOG TIMER REGISTERS

Six Peripheral Control Block Registers control the Watchdog Timer Unit. The Watchdog Timer
Reload Value is held in two 16-bit registers: WDTRLDH (Figure 12-5) and WDTRLDL (Figure
12-6). The value in the 32-bit down counter can be read from the count registers, WDTCNTH
(Figure 12-7) and WDTCNTL (Figure 12-8). The count registers are read only.
The WDT Clear (WDTCLR) and WDT Disable (WDTDIS) registers are not shown, as their func-
tions are described in the text and are not tied to specific bit positions. "Reloading the Watchdog
Timer Down Counter" on page 12-3 describes the WDT Clear register, and "Disabling the
Watchdog Timer" on page 12-6 discusses the WDT Disable register.
12-8
055H, 0AAH
XXXXH
?
ax, seg wdt_off
ds, ax
si, offset wdt_off
ax, seg WDTDIS
es, ax
di, offset WDTDIS
cx, 2
;replace "XXXX" with appropriate
;offset from PCB+0.
;DS:SI = address of disable
;value for the WDT
;ES:DI = address of WDTDIS register
;clear direction flag(autoincrement)
;2 bytes in sequence
;LOCKed disable sequence
;The WDT down counter
;has been disabled.

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