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OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE
Numerics Coprocessor Fault — Type 16
The Numerics Coprocessor fault is caused by an external 80C187 numerics coprocessor. The
80C187 reports the exception by asserting the ERROR pin. The 80C186 Modular Core checks
the ERROR pin only when executing a numerics instruction. A Numerics Coprocessor Fault in-
dicates that the previous numerics instruction caused the exception. The 80C187 saves the ad-
dress of the floating point instruction that caused the exception. The return address pushed onto
the stack during the interrupt processing points to the numerics instruction that detected the ex-
ception. This way, the last numerics instruction can be restarted.
2.3.2
Software Interrupts
A Software Interrupt is caused by executing an "INTn" instruction. The n parameter corresponds
to the specific interrupt type to be executed. The interrupt type can be any number between 0 and
255. If the n parameter corresponds to an interrupt type associated with a hardware interrupt
(NMI, Timers), the vectors are fetched and the routine is executed, but the corresponding bits in
the Interrupt Status register are not altered.
The CPU processes software interrupts and exceptions in the same way. Software interrupts, ex-
ceptions and traps cannot be masked.
2.3.3
Interrupt Latency
Interrupt latency is the amount of time it takes for the CPU to recognize the existence of an inter-
rupt. The CPU generally recognizes interrupts only between instructions or on instruction bound-
aries. Therefore, the current instruction must finish executing before an interrupt can be
recognized.
The worst-case 80C186 instruction execution time is an integer divide instruction with segment
override prefix. The instruction takes 69 clocks, assuming an 80C186 Modular Core family mem-
ber and a zero wait-state external bus. The execution time for an 80C188 Modular Core family
member may be longer, depending on the queue.
This is one factor in determining interrupt latency. In addition, the following are also factors in
determining maximum latency:
1.
The CPU does not recognize the Maskable Interrupt unless the Interrupt Enable bit is set.
2.
The CPU does not recognize interrupts during HOLD.
3.
Once communication is completely established with an 80C187, the CPU does not
recognize interrupts until the numerics instruction is finished.
2-44
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