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CHAPTER 4
PERIPHERAL CONTROL BLOCK
4.1
PERIPHERAL CONTROL REGISTERS........................................................................ 4-1
4.2
PCB RELOCATION REGISTER.................................................................................... 4-1
4.3
RESERVED LOCATIONS ............................................................................................. 4-4
4.4
ACCESSING THE PERIPHERAL CONTROL BLOCK .................................................. 4-4
4.4.1
Bus Cycles ...............................................................................................................4-4
4.4.2
READY Signals and Wait States .............................................................................4-4
4.4.3
F-Bus Operation .......................................................................................................4-5
4.4.3.1
Writing the PCB Relocation Register ...............................................................4-6
4.4.3.2
Accessing the Peripheral Control Registers ....................................................4-6
4.4.3.3
Accessing Reserved Locations .......................................................................4-6
4.5
SETTING THE PCB BASE LOCATION......................................................................... 4-6
4.5.1
Considerations for the 80C187 Math Coprocessor Interface ....................................4-7
CHAPTER 5
CLOCK GENERATION AND POWER MANAGEMENT
5.1
CLOCK GENERATION.................................................................................................. 5-1
5.1.1
Crystal Oscillator .......................................................................................................5-1
5.1.1.1
Oscillator Operation .........................................................................................5-2
5.1.1.2
Selecting Crystals ............................................................................................5-5
5.1.2
Using an External Oscillator ......................................................................................5-6
5.1.3
Output from the Clock Generator ..............................................................................5-6
5.1.4
Reset and Clock Synchronization .............................................................................5-6
5.2
POWER MANAGEMENT............................................................................................. 5-10
5.2.1
Idle Mode ................................................................................................................5-11
5.2.1.1
Entering Idle Mode ........................................................................................5-11
5.2.1.2
Bus Operation During Idle Mode ...................................................................5-13
5.2.1.3
Leaving Idle Mode .........................................................................................5-14
5.2.1.4
Example Idle Mode Initialization Code ..........................................................5-15
5.2.2
Powerdown Mode ...................................................................................................5-16
5.2.2.1
Entering Powerdown Mode ...........................................................................5-17
5.2.2.2
Leaving Powerdown Mode ............................................................................5-18
5.2.3
Power-Save Mode ..................................................................................................5-19
5.2.3.1
Entering Power-Save Mode ..........................................................................5-20
5.2.3.2
Leaving Power-Save Mode ...........................................................................5-22
5.2.3.3
Example Power-Save Initialization Code .......................................................5-22
5.2.4
Implementing a Power Management Scheme ........................................................5-24
CHAPTER 6
CHIP-SELECT UNIT
6.1
COMMON METHODS FOR GENERATING CHIP-SELECTS....................................... 6-1
6.2
CHIP-SELECT UNIT FEATURES AND BENEFITS ...................................................... 6-1
6.3
CHIP-SELECT UNIT FUNCTIONAL OVERVIEW ......................................................... 6-2
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