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Register Name:
Register Mnemonic:
Register Function:
15
Bit
Bit Name
Mnemonic
SBRK
Send Break
TB8
Transmitted
Bit 8
CEN
Clear-to-
Send Enable
REN
Receive
Enable
EVN
Even Parity
Select
PEN
Parity
Enable
M2:0
Serial Port
Mode Field
NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written to
a logic zero to ensure compatibility with future Intel products.
Figure 11-13. Serial Port Control Register (SxCON)
Serial Port Control Register
SxCON
Controls serial port operating modes.
S
T
C
R
B
B
E
E
R
8
N
N
K
Reset
State
0
Setting SBRK drives TXD low. TXD remains low
until SBRK is cleared.
0
TB8 is the eighth data bit transmitted in modes 2
and 3.
0
When CEN is set, no transmissions will occur until
the CTS pin is asserted.
0
Set to enable the receive machine.
0
When parity is enabled, EVN selects between even
and odd parity. Set for even, clear for odd parity.
0
Setting PEN enables the parity generation/checking
for all transmissions/receptions.
0
Operating mode for the serial port channel.
M2
M1
M0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
SERIAL COMMUNICATIONS UNIT
E
P
M
M
M
V
E
2
1
0
N
N
Function
Mode
Synchronous Mode0
10-Bit Asynch Mode1
11-Bit Asynch Mode2
11-Bit Asynch Mode3
9-Bit Asynch Mode4
Reserved
Reserved
Reserved
0
A1277-0A
11-15
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