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INTERRUPT CONTROL UNIT
8.3.2.3
Spurious Interrupts
For both level- and edge-sensitive interrupts, a high value must be maintained on the IR line until
after the falling edge of the second INTA pulse (see Figure 8-5). A spurious interrupt request is
generated if this stipulation is not met. A spurious interrupt on any IR line generates the same
vector as an IR7 request. However, a spurious interrupt does not set the In-Service bit for IR7
when it is acknowledged by the CPU. The interrupt handler for IR7 must check the In-Service
Register to determine whether the interrupt source was a valid IR7 (the In-Service bit is set) or a
spurious interrupt (the In-Service bit is cleared).
INTA
IR (Spurious)
IR (Valid)
8.3.3
The Priority Resolver and Priority Resolution
The Priority Resolver uses four pieces of information when deciding whether to generate a CPU
interrupt:
•
the programmed operating mode and priority structure
•
the state of the bits in the Interrupt Request Register
•
the state of the bits in the In-Service Register
•
the state of the bits in the Interrupt Mask Register
The priority scheme used by the Priority Resolver is programmable. The remainder of this section
describes the priority structure options.
8-10
IR sampled on this edge.
Figure 8-5. Spurious Interrupts
A1241-0A
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