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INDEX
Trap exceptions, 2-42
Trap Flag (TF), 2-7, 2-9, 2-43, 2-48
T-state
and bus cycles, 3-9
and CLKOUT, 3-8
defined, 3-7
W
Wait states
and bus cycles, 3-13
and chip-selects, 6-11–6-14
and DRAM controllers, 7-1
and external 82C59A device, 8-46
and ICU, 8-44
and PCB accesses, 4-4
and READY input, 3-13
Watchdog Timer (WDT) Unit, 12-1–12-13
and Interrupt Control Unit, 12-2
block diagram, 12-2
disabling, 12-6–12-8
down counter, reloading, 12-1, 12-3, 12-4
generating interrupts, 12-3
initializing, 12-5
output waveforms, 12-6
overview, 12-1–12-2
registers, 12-8–12-13
reset circuit, 12-2
using as general-purpose timer, 12-6
using as watchdog, 12-1–12-5
WDT Count Value Register, 12-11, 12-12
WDT Reload Value Register, 12-9, 12-10
Word integer, defined, 14-7
World Wide Web, 1-6
Write bus cycle, 3-23
Z
Zero Flag (ZF), 2-7, 2-9, 2-23
Index-10
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