Table of Contents
Advertisement
P
Packed BCD, defined, 2-37
Packed decimal, defined, 14-7
Parity Flag (PF), 2-7, 2-9
PCB Relocation Register, 4-1, 4-3, 4-6
and math coprocessing, 14-1
PDTMR pin, 5-18
Peripheral Control Block (PCB), 4-1
8259A register access ports, 8-21
accessing, 4-4
and DMA Unit, 10-3
and F-Bus operation, 4-5
base address, 4-6–4-7
bus cycles, 4-4
READY signals, 4-4
reserved locations, 4-6
wait states, 4-4
Peripheral control registers, 4-1, 4-6
Pointer, defined, 2-37
Poll Status Byte, 8-35
Polling
and 8259A initialization, 8-35
overview, 8-3
with the Poll command, 8-20, 8-34
POPA instruction, A-1
Port Control Register (PxCON), 13-8
Port Data Latch Register (PxLTCH), 13-10
Port Direction Register (PxDIR), 13-9
Port Pin State Register (PxPIN), 13-11
Power consumption‚ reducing, 3-29, 5-24
Power Control Register, 5-12
Power management, 5-10–5-24
Power management modes
and HALT bus cycles, 3-29, 3-32, 3-34
compared, 5-24
Powerdown mode, 5-16–5-19, 7-2
and bus cycles, 5-16
control register, 5-12
entering, 5-17
exiting, 5-18–5-19
exiting HALT bus cycle, 3-35
initialization code, 5-15–5-19
Power-Save mode, 5-19–5-23, 7-2
and DRAM refresh rate, 5-22
and refresh interval, 7-7
control register, 5-21
entering, 5-20
exiting, 5-22
initialization code, 5-22–5-23
Power-Save Register, 5-21
Priority cell‚ See Interrupts
Priority Resolver, 8-10
Processor control instructions, 2-27
Processor Status Word (PSW), 2-1, 2-7, 2-41
bits defined, 2-7, 2-9
flag storage formats, 2-19
reset status, 2-7
Program transfer instructions, 2-23–2-24
conditional transfers, 2-24, 2-26
interrupts, 2-26
iteration control, 2-25
unconditional transfers, 2-24
Programming examples‚ See Software
PUSH instruction, A-8
PUSHA instruction, A-1
R
RCL instruction, A-10
RCR instruction, A-10
Read bus cycles‚ See Bus cycles
READY
and chip-selects, 6-11
and internal 8259A modules, 8-44
and normally not-ready signal, 3-16–3-18
and normally ready signal, 3-16–3-17
and PCB accesses, 4-4
and wait states, 3-13–3-18
block diagram, 3-15
implementation approaches, 3-13
timing concerns, 3-17
Real, defined, 14-7
Real-time clock, code example, 9-17–9-20
Refresh address, 7-4
Refresh Address Register (RFADDR), 7-10
Refresh Base Address Register (RFBASE), 7-8
Refresh bus cycle‚ See Bus cycles
Refresh Clock Interval Register (RFTIME), 7-7,
7-8
Refresh Control Register (RFCON), 7-9, 7-10
Refresh Control Unit (RCU), 7-1–7-14
and bus hold protocol, 7-13–7-14
and Powerdown mode, 7-2
and Power-Save mode, 5-20, 7-2, 7-7
block diagram, 7-1
INDEX
Index-7
Advertisement
Table of Contents
