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Register Name:
Register Mnemonic:
Register Function:
15
E
I
I
N
N
N
H
T
Bit
Bit Name
Mnemonic
EN
Enable
INH
Inhibit
INT
Interrupt
RIU
Register In
Use
MC
Maximum
Count
NOTE: Reserved register bits are shown with gray shading. Reserved bits must be written to a
logic zero to ensure compatibility with future Intel products.
Figure 9-5. Timer 0 and Timer 1 Control Registers
Timer 0 and 1 Control Registers
T0CON, T1CON
Defines Timer 0 and 1 operation.
R
I
U
Reset
State
0
Set to enable the timer. This bit can be written only
when the INH bit is set.
X
Set to enable writes to the EN bit. Clear to ignore
writes to the EN bit. The INH bit is not stored; it
always reads as zero.
X
Set to generate an interrupt request when the Count
register equals a Maximum Count register. Clear to
disable interrupt requests.
X
Indicates which compare register is in use. When set,
the current compare register is Maxcount Compare B;
when clear, it is Maxcount Compare A.
X
This bit is set when the counter reaches a maximum
count. The MC bit must be cleared by writing to the
Timer Control register. This is not done automati-
cally. If MC is clear, the counter has not reached a
maximum count.
TIMER/COUNTER UNIT
M
R
P
E
A
C
T
X
L
G
T
T
Function
0
C
O
N
T
A1297-0A
9-7
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