Intel 80C188EC User Manual page 370

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A LOCKed instruction sequence that is similar to the reload sequence disables the Watchdog
Timer. The Watchdog Timer Disable (WDTDIS) Register expects a sequence of two bytes,
which must be written by a single LOCKed instruction. The first byte must be 55H and the second
must be 0AAH (the reverse of the reload sequence). Writing any other data values or using two
separate LOCKed instructions will not disable the WDT. The Watchdog Timer cannot be dis-
abled once it has been reloaded by the system software. Similarly, it cannot be enabled once it
has been disabled.
Examples 12-3 and 12-4 show the code necessary to disable the Watchdog Timer Unit when the
Peripheral Control Block is located in I/O and memory space, respectively.
wdt_data
segment
wdt_off
DB
wdt_data
ends
wdt_code
segment
assume cs:wdt_code
mov
mov
mov
mov
cld
mov
lock rep
outsb
wdt_code
ends
Example 12-3. Disabling the Watchdog Timer (Peripheral Control Block in I/O Space)
055H, 0AAH
ax, seg wdt_off
es, ax
si, offset wdt_off
dx, WDTDIS
cx, 2
es:[si], dx
WATCHDOG TIMER UNIT
;ES:SI points to wdt_key
;disable value of WDT
;clear direction flag (autoincrement)
;2 bytes will be written
;LOCKed disable sequence.
;The WDT is disabled
12-7

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