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BUS INTERFACE UNIT
CLKOUT
S2:0
ALE
A19:16
A15:8
BHE
RFSH
A15:0
[AD7:0]
RD
DT / R
DEN
3.5.1.1
Refresh Bus Cycles
A refresh bus cycle operates similarly to a normal read bus cycle except for the following:
•
For a 16-bit data bus, address bit A0 and BHE drive to a 1 (high) and the data value on the
bus is ignored.
•
For an 8-bit data bus, address bit A0 drives to a 1 (high) and RFSH is driven active (low).
The data value on the bus is ignored. RFSH has the same bus timing as BHE.
3-22
T1
T2
Status Valid
Address Valid
Address
Valid
Figure 3-19. Typical Read Bus Cycle
T3
T4
A18:16 = 0, A19=Valid Status
Valid
Data
Valid
A1084-0A
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