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The address/status phase starts just before T1 and continues through T1. The data phase starts at
T2 and continues through T4. Figure 3-9 illustrates the T-state relationship of the two phases.
T1
Request Pending
HOLD Deasserted
T4
Halt Bus Cycle
T2
TI
RESIN
Asserted
HOLD Asserted
Figure 3-8. BIU State Diagram
BUS INTERFACE UNIT
Bus Ready
Request Pending
HOLD Deasserted
T3
Bus Not
Ready
Bus Ready
No Request Pending
HOLD Deasserted
A1538-01
3-9
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