Programming The Dma Unit - Intel 80C188EC User Manual

Channel arbitration within the DMA Unit first begins on the module level. Each module priori-
tizes its two DMA requests (if active) and then presents a module request to the Inter-Module Ar-
bitration Logic. If both modules are requesting transfers, the Inter-Module Arbitration Logic
decides which of the two modules has highest priority and grants that module control of the bus.

10.2 PROGRAMMING THE DMA UNIT

A total of six Peripheral Control Block registers configure each DMA channel. Two additional
registers are used to specify parameters for inter-module priority, internal DMA request multi-
plexing and DMA suspension.
10.2.1 DMA Channel Parameters
The first step in programming the DMA Unit is to set up the parameters for each channel.
10.2.1.1 Programming the Source and Destination Pointers
The following parameters are programmable for the source and destination pointers:
•
pointer address
•
address space (memory or I/O)
•
automatic pointer indexing (increment, decrement or no change) after transfer
Two 16-bit Peripheral Control Block registers define each of the 20-bit pointers. Figures 10.7 and
10.8 show the layout of the DMA Source Pointer address registers, and Figures 10.9 and 10.10
show the layout of the DMA Destination Pointer address registers. The DSA19:16 and
DDA19:16 (high-order address bits) are driven on the bus even if I/O transfers have been pro-
grammed. When performing I/O transfers within the normal 64K I/O space only, the high-order
bits in the pointer registers must be cleared.
DIRECT MEMORY ACCESS UNIT
10-15