Table of Contents
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Table
1-1
Comparison of 80C186 Modular Core Family Products ...............................................1-2
1-2
Related Documents and Software................................................................................1-3
2-1
Implicit Use of General Registers .................................................................................2-5
2-2
Logical Address Sources............................................................................................2-13
2-3
Data Transfer Instructions ..........................................................................................2-18
2-4
Arithmetic Instructions ................................................................................................2-20
2-5
Arithmetic Interpretation of 8-Bit Numbers .................................................................2-21
2-6
Bit Manipulation Instructions ......................................................................................2-21
2-7
String Instructions.......................................................................................................2-22
2-8
String Instruction Register and Flag Use....................................................................2-23
2-9
Program Transfer Instructions ....................................................................................2-25
2-10
Interpretation of Conditional Transfers .......................................................................2-26
2-11
Processor Control Instructions ...................................................................................2-27
2-12
Supported Data Types ...............................................................................................2-37
3-1
Bus Cycle Types ........................................................................................................3-12
3-2
Read Bus Cycle Types ...............................................................................................3-20
3-3
Read Cycle Critical Timing Parameters......................................................................3-21
3-4
Write Bus Cycle Types ...............................................................................................3-24
3-5
Write Cycle Critical Timing Parameters......................................................................3-26
3-6
HALT Bus Cycle Pin States........................................................................................3-30
3-7
Signal Condition Entering HOLD ................................................................................3-42
4-1
Peripheral Control Block...............................................................................................4-3
5-1
Suggested Values for Inductor L
5-2
Summary of Power Management Modes ...................................................................5-24
6-1
Chip-Select Unit Registers ...........................................................................................6-5
6-2
Memory and I/O Compare Addresses ........................................................................6-10
6-3
Example Adjustments for Overlapping Chip-Selects..................................................6-14
7-1
Identification of Refresh Bus Cycles.............................................................................7-5
8-1
Operation Command Word Addressing......................................................................8-30
8-2
OCW2 Instruction Field Decoding ..............................................................................8-32
9-1
Timer 0 and 1 Clock Sources .....................................................................................9-12
9-2
Timer Retriggering......................................................................................................9-13
10-1
DMA Unit Naming Conventions and Signal Connections.........................................10-13
11-1
BxCMP Values for Typical Baud Rates and CPU Frequencies................................11-13
13-1
Port 1 Multiplexing Options ........................................................................................13-6
13-2
Port 2 Multiplexing Options ........................................................................................13-6
13-3
Port 3 Multiplexing Options ........................................................................................13-7
14-1
80C187 Data Transfer Instructions.............................................................................14-3
14-2
80C187 Arithmetic Instructions...................................................................................14-4
14-3
80C187 Comparison Instructions ...............................................................................14-5
14-4
80C187 Transcendental Instructions..........................................................................14-5
14-5
80C187 Constant Instructions ....................................................................................14-6
14-6
80C187 Processor Control Instructions......................................................................14-6
14-7
80C187 I/O Port Assignments ..................................................................................14-10
TABLES
in Third Overtone Oscillator Circuit.........................5-4
1
CONTENTS
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