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SERIAL COMMUNICATIONS UNIT
The Transmit machine can be disabled by an external source by using the Clear-to-Send feature.
When the Clear-to-Send feature is enabled, the TX machine will not transmit until the CTS pin
is asserted. The CTS pin is level sensitive. Asserting the CTS pin before a pending transmission
for at least 1½ clock cycles ensures that the entire frame will be transmitted. See "CTS Pin Tim-
ings" on page 11-18 for details.
The TX machine can also transmit a break character. Setting the SBRK bit forces the TXD pin
immediately low. The TXD pin remains low until the user clears SBRK. The TX machine will
continue the transmission sequence even if SBRK is set. Use caution when setting SBRK or char-
acters will be lost.
11.1.1.3
Modes 1, 3 and 4
The three asynchronous modes of the serial ports, Modes 1, 3 and 4, operate in approximately the
same manner. Mode 1 is the 8-bit asynchronous communications mode. Each frame consists of
a start bit, eight data bits and a stop bit, as shown in Figure 11-4. When parity is used, the eighth
data bit becomes the parity bit. Both the RX and TX machines use this frame in Mode 1 with no
exceptions.
Mode 3 is the 9-bit asynchronous communications mode (see Figure 11-5). Mode 3 is the same
as Mode 1 except that a frame contains nine data bits. The ninth data bit becomes the parity bit
when the parity feature is enabled. When parity is disabled, the ninth data bit is controlled by the
user. (See "Modes 2 and 3 for Multiprocessor Communications" on page 11-14.) Mode 3 can be
used with Mode 2 for multiprocessor communications or alone for "8 data bits + parity" frames.
Mode 4 is the 7-bit asynchronous communications mode. Each frame consists of a start bit, seven
data bits and a stop bit, as shown in Figure 11-6. Parity is not available in Mode 4. Both the RX
and TX machines use this frame in Mode 4 with no exceptions.
2
1
TXD/
Start
Bit 0
RXD
Bit
11-6
3
4
5
Bit 1
Bit 2
Bit 3
Figure 11-4. Mode 1 Waveform
6
7
8
Bit 4
Bit 5
Bit 6
9
10
Parity
Stop
or
Bit
Bit 7
A1285-0A
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