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INPUT SYNCHRONIZATION
A synchronization failure can occur when the output of the first latch does not meet the setup and
hold requirements of the input of the second latch. The rate of failure is determined by the actual
size of the sampling window of the data latch and by the amount of time between the strobe sig-
nals of the two latches. As the sampling window gets smaller, the number of times an asynchro-
nous transition occurs during the sampling window drops.
B.2
ASYNCHRONOUS PINS
The 80C186EC/80C188EC inputs that use the two-stage synchronization circuit are T0IN, T1IN,
NMI, TEST/BUSY, INT7:0, HOLD, all port pins used as inputs, and DRQ3:0.
B-2
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