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CHIP-SELECT UNIT
BUS READY
READY Control Bit
READY
Wait
Wait
Wait State Value (WS3:0)
State
State
Counter
Ready
A1165-0A
Figure 6-7. Wait State and Ready Control Functions
The STOP register defines the RDY control bit to extend bus cycles beyond fifteen wait states.
The RDY control bit determines whether the bus cycle should complete normally (i.e., require
bus ready) or unconditionally (i.e., ignore bus ready). Chip-selects connected to devices requiring
fifteen wait states or fewer can program RDY inactive to automatically complete the bus cycle.
Devices that may require more than fifteen wait states must program RDY active.
A bus cycle with wait states automatically inserted cannot be shortened. A bus cycle that ignores
bus ready cannot be lengthened.
6.4.6
Overlapping Chip-Selects
The Chip-Select Unit activates all enabled chip-selects programmed to cover the same physical
address space. This is true if any portion of the chip-selects' address ranges overlap (i.e., chip-
selects' ranges do not need to overlap completely to all go active). There are various reasons for
overlapping chip-selects. For example, a system might have a need for overlapping a portion of
read-only memory with read/write memory or copying data to two devices simultaneously.
If overlapping chip-selects do not have identical wait state and bus ready programming, the Chip-
Select Unit will adjust itself based on the criteria shown in Figure 6-8.
6-12
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